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Renesas Electronics /R7FA6M3AH /GLCDC /TCON_STVB2

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Interpret as TCON_STVB2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)SEL0 (0)INV

INV=0, SEL=000

Description

TCON Vertical Timing Setting Register B2

Fields

SEL

Output signal select control for VSOUT (controlled by TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 register) pin

0 (000): STVA

1 (001): STVB

2 (010): STHA

3 (011): STHB

4 (100): Setting prohibited

5 (101): Setting prohibited

6 (110): Setting prohibited

7 (111): DE
INV

STVx signal polarity inversion control

0 (0): Not inverted

1 (1): Inverted

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data